The six most important things I learned about Zen 6 and Zen 6c at AMD In Depth in Las Vegas

TechFinitive was lucky enough to score an invite to AMD In Depth in Las Vegas last week. The event’s focus: a deep dive into the all-new AMD EPYC Venice processors, the first to be powered by AMD’s Zen 6 and Zen 6c architecture. I won’t bombard you with every detail from our two days of briefings. Instead, this article concentrates on the six most important takeaways about the Zen 6 and Zen 6c cores.

Before I dive in, it’s important to have a wider view of what Zen 6 means. Not only will this microarchitecture power the new generation of AMD EPYC processors (used in servers and data centres), but also the Ryzen desktop and laptop chips that will almost certainly be released in early 2027.

Most of these insights came from an in-depth talk by Michael Clark, the Chief Architect of CPUs at AMD and “the original Zen architect”, to use his own words. Please also note that a few of the technical details here have either been hinted at or announced in previous AMD briefings.

Summary of Zen 6-powered AMD chips

AMD considers Zen 6c a performance offering

With the Zen 5 architecture, AMD positioned Zen 5 cores as the performance choice with Zen 5c there to provide efficient support. It’s an approach that Intel followed with its chips: performant P-cores, efficient E-cores, low-power efficient LPE-cores. But Zen 6 marks a shift.

“We now have quadruple the cache in the complex that we used to have with our Zen 5c core,” said Clark. “We’ve now gone from 32MB to 128MB available to that Zen 6c core.” (A “complex” is a group of cores that share local cache.)

So why does AMD still offer two types of core? Because the Zen 6 is faster. As you can see in the summary table below, it peaks at 5.3GHz compared to 4.1GHz for the Zen 6c cores.

“Frequency is still part of the equation, right?” said Clark. “That wheel still matters. Even though we have so many cores, we don’t want customers to have to fill up 256 cores to get the maximum throughput.”

In short, Zen 6c will be perfectly suited to tasks that benefit from multiple threads (both Zen 6 and Zen 6c still support simultaneous multithreading (SMT), so 12 cores equates to 24 threads) while Zen 6 is the best choice for workloads that need maximum throughput and minimum latency. Gaming being one obvious example.

The new chips are great for agentic AI workloads… but luck was in play

When AMD started designing Zen 6, roughly four years ago, AI was a niche technology. The term artificial intelligence was almost stigmatised, associated with over-blown promises and science fiction. Then ChatGPT happened, ushering us into the AI era via chatbots that actually answered questions.

As we enter the next phase of AI, summarised by the term agentic AI, AMD believes it has the answer thanks to Zen 6 and Zen 6c. In particular through its variety of EPYC Venice processors, which AMD has already announced will power part of the Microsoft Azure estate.

“I’m not going to mislead and act like I knew agentic computing was coming, or we knew it, but we did strongly believe that the CPU would always have a place in the software ecosystem of AI,” said Clark. “And so, even with Zen 5, we really did lay a new foundation, kind of drive forward AI, and so we knew for Zen 6, we wanted to enhance AI capabilities, enhance the core, so that as agentic AI has blown up, we’re able to deploy that for agentic compute workloads.”

Benchmarks suggest huge uplift, but it depends on the workload

No need for many words here: the picture tells its own clear story. Obviously AMD has chosen its own benchmarks, but it’s aimed to make it as apples vs apples as possible by standardising on 16 cores. And note these figures are instruction per clock, and Zen 5 has a higher frequency than Zen 6c, so it will make up some of that gap by clock speed alone.

However, the point stands. The Zen 6c is more than a match for the Zen 5, and as far more cores can be squeezed into the a single processor – up to 256 versus 64 for the Zen 5 – you can expect a serious amount of consolidation if replacing an older server. If it’s five years old, AMD reckons it will a consolidation ratio of roughly 12:1.

Power efficiency is arguably the biggest gain

Both the Zen 6 and Zen 6c will be built on TSMC’s N2 process, so 2nm rather than 3nm and 4nm for the Zen 5 and Zen 5c respectively. That immediately improves power efficiency (and the number of cores you can squeeze into a core complex), but other factors also contribute.

“We’re really focused on Zen 6 on getting also that power efficiency, getting more work done in the same area,” said Clark. “So we really optimised those branch prediction tables so we could get better predictions.”

I will leave other more technical sites to delve deep into this technology, but the essence is this. By better predictions, Clark means you waste less time fetching data and you can execute more operations per cycle. (And much more besides, but let’s not go down that rabbit hole.)

With Zen 6/Zen 6c, AMD has also added more instructions into hardware, which means less needs to happen on software. While this only results in energy savings if the instructions are called into action, they almost certainly will in this case: full FP16 support is particularly notable as it’s used for deep learning workloads.

Security is built into the heart of this CPU

Clark was also keen to point out Zen 6’s security benefits. “The first feature is RMPOPT. The secure guests [on the hypervisor] use an RMP table to protect themselves,” he said. “This actually causes non-secure guests running in the same environment to have to do extra checks, or we have to do extra checks to prevent them from crossing the boundary of the secure guests.”

Clark explained that caused a big overhead in a mixed environment. “So we now have a way for the OS to tell us about these pages at a larger scale, so we can quickly reduce the penalty of unsecure guests running in a secure environment.”

AMD also added a “DIRTY bit optimization, so live migration again is easier within this the confidential compute environment as you’re moving guests around.”

And while previous generations had had SMT [simultaneous multithreading] protection within the architecture, “it really only protected you by not having anyone else next to you in the same core”, said Clark. With Zen 6, you can run them “next to each other” and still benefit from the full performance and benefits that SMT offers.

AMD doesn’t use AI to help design its chips (yet)

At the end of the first day’s session, we were invited to ask the AMD grandees (all men, by the way) any questions. Many focused on AMD MEXT, which makes sense as we are still in the midst of a memory crisis and this looks to be a revolutionary technology.

I decided to use this opportunity to ask how AMD is currently using AI to improve its own chip design, as the block diagrams we’d been shown during the day were little different to what came before.

“Everyone is using AI,” said Dan McNamara, General Manager of Compute and Enterprise AI, adding that AMD’s engineers always have too many ideas on how to improve chips than they can explore. “We can get through a lot more ideas, and we can get rid of bad ideas quicker.”

Then there are “simple things like documentation. The engineers hate documenting stuff, so that task is offloaded.” Another area was verification, he added, with “massive, massive deployment of AI” now determining the cause of problems. “So our engineers that are working on the future have wasted a lot of time on the past trying to figure out what’s wrong.”

But, he conceded, “if you look at my block diagram, it doesn’t look much different. But all the things underneath are allowing us to go faster, be more innovative, and when we have them, those are the things we don’t tell you about because there are secrets. So there’s so much in there I’m already not telling you. AI is making even more of them.”