What is Intel Xeon 6+ in Intel’s own words

Last week I attended an event in Arizona where Intel unveiled Clearwater Forest. This is the all-new Xeon 6+ E-core product aimed at cloud service providers and telcos. It’s going to be the second chip based on Intel’s 18A process, with the chips proudly made in the USA – specifically in Arizona and Oregon.

This article aims to tell you exactly what you need to know about Clearwater Forest in Intel’s own words. It’s based on several briefings I attended during the Intel Tech Tour US 2025, which also included a trip to Fab 52 where Clearwater Forest/Xeon E-core processors are made. I’ll also throw in a few slides from the presentations.

Enjoy!

A Clearwater Forest/Xeon E-core processor (image: Intel)
A Clearwater Forest/Xeon E-core processor (image: Intel)

What is Intel Xeon 6+

Codenamed Clearwater Forest, Intel Xeon 6+ is an addition to the Xeon 6 family of products geared towards telcos and cloud service providers. Its all about efficiency: delivering the consistent level of power such services need with minimum wattage.

“We’re naming the platform Xeon 6+,” said Kevork Kechichian, the newly appointed General Manager of the Intel Data Center Group, “which of course [builds on the lineage] of all the Xeon 6 deployments that we have, the products we have.

“You’ll see that it’s a significant additive on the existing Xeon 6 platform. It’s not just in micro architecture improvements, the density of the cores, but also increased bandwidth, increased core counts. And most importantly, this our own 18A technology.”

Intel Xeon 6+ slide
That gap top right suggests a Xeon 6+ with P-cores will surely come in the future (image: Intel)

Why did Intel build the Xeon 6+

“When we started building Clearwater Forest, we first asked our customers, what is it you most want out of this generation?” said Kira Boyko, Product Line Director of Intel’s E-Core Xeon Products.

“We were told a couple things. First of all, they wanted it to be the highest performant per core Xeon that we have available… Second, they want it to be the highest efficiency, so highest performance per watt.

“And then finally, they said, and this is especially from our OEMs, we don’t want to have to build a new server specifically for this product. Please build something that is socket compatible with the existing Granite Rapids AP [Advanced Performance] so that we can take this product, drag and drop it into our existing server and deploy out to our customers as quickly as possible.”

What challenges face telecoms operators in particular?

“I want to frame the problem from a telecom operator perspective, so the key challenges that they face are highlighted on the slide,” said an Intel Product Director whose name I unfortunately didn’t catch.

“So the first one is the traffic in the network is growing at a very good pace. We are facing both number of sessions growing as well as data growth in the network,” he added. “The budget for power and space remains limited, so they are facing a double edge challenge.

“At the same time, since these are mission-critical infrastructures, their deployments need double-zero downtime as well as hard and secure systems, so there’s very little room for mistakes. And they are very worried about the increasing OPEX cost.

“The other challenge they face is that they need to scale this workload in a cloud-native environment with micro services. So they need an architecture that can scale easily with those workloads. And so they need to address all of these challenges without rewriting the existing stack.”

What performance improvements can you expect?

“From a performance perspective, we started out by doubling the core count,” said Bokyo. “So Sierra Forest [Xeon 6 E-core released last year] topped out at 144 cores. Clearwater Forest is 288.”

Intel has also increased the performance of the cores, having switched to “Darkmont”.

Xeon 6+ compute tile architecture
Each compute tile features 24 Darkmont E-cores (image: Intel)

“Each of those cores is delivering 17% more IPC [instruction per clock] than the last generation,” said Tim Wilson, General Manager of Intel’s Datacenter Silicon Engineering group. “We’ve increased the shared last level cache by more than 5x and to support all of this new compute capability in the socket, we’ve increased the memory IO channels and capability by 50% generation on generation, while at the same time increasing the memory frequency itself by 20% to eight bigger transit.”

Slide comparing Crestmont E-cores with Darkmont E-cores
How Intel achieved the 17% IPC uplift (image: Intel)

Bokyo added: “So Sierra Forest was eight channels up to 6400 [up to 6400MT/sec throughput]. For Clearwater forest, we went even higher, up to 12 channels on 8000.

“Now, when it launches, which is the first half of next year, it’s possible that 8000 might not be broadly adopted in the market so we’re going to be supporting lower [speeds] as well.”

What about efficiency improvements

The Intel 18A process is a crucial part of what makes Xeon 6+ power efficient (image: Intel)

“This architecture delivers measurable, real-world customer experience for a customer upgrading a data centre that’s five years old, “said Wilson. “This represents an 8x server consolidation opportunity, which translates to 750 kilowatts power savings.

“At the same time, they can reduce the floor plan, the fleet space footprint in the data centre by over 70% while getting three and a half times performance-per-watt improvement.”

Much of the efficiency stems from Intel’s 18A process, which is too deep a topic to delve into here. Suffice to say that the drop in process size, together with a number of power-friendly enhancements, all help to improve the efficiency of the Xeon 6+ compared to Xeon 6 E-core (which was built on the Intel 3 process).

Boyko also pointed to Intel’s AET technology, standing for Application Energy Telemetry.

“It’s going to allow our end customers to follow a workload on a per-thread basis as it moves from core to core, so that the customer can then orchestrate where they want it to run for optimum energy efficiency,” she said.

“You’re going to be able to say, as the operator not the end customer – or whoever’s doing the software stack for that end customer – they’re going to be able to say, ‘Hey, I save more energy if I run this workload for this customer, on this thread, on this core, so I’m going to orchestrate so that it stays there to keep cost down, energy down.”

Avatar photo
Tim Danton

Tim has worked in IT publishing since the days when all PCs were beige, and is editor-in-chief of the UK's PC Pro magazine. He has been writing about hardware for TechFinitive since 2023.